Investigation of L-shaped split-gate eFlash memory with enhanced gate coupling in a 55 nm node

As data processing demands increase, embedded flash is advancing toward low power consumption, low manufacturing cost, and high operation speed, as well as large memory windows (MW). A self-aligned split-gate floating-gate (FG) NOR-type flash memory cell and array have been proposed under a 55 nm node. Low-voltage erase and high-speed program operation have been achieved owing to a low EP-to-FG coupling ratio of 0.09 and a high CG-to-FG coupling ratio of 0.67, respectively. Moreover, up to 8 masks can be reduced in our low-cost process, as compared to that of the third-generation SuperFlash. Additionally, close to 5-bit states have been realized in the large MW of 7.1 V in a single-bit cell, which is mostly attributed to the threshold voltage (Vth) tuning by drain-side dual-pocket implantation.