总谐波失真
无杂散动态范围
计算机科学
线性
抖动
电子工程
动态范围
CMOS芯片
失真(音乐)
噪音(视频)
高动态范围
滤波器(信号处理)
噪声整形
过调制
偏压
转换器
数字音频
谐波
数字滤波器
信噪比(成像)
压扩
数模转换器
稳健性(进化)
电压
三角积分调变
宽动态范围
航程(航空)
采样(信号处理)
控制理论(社会学)
微分非线性
计算机硬件
电阻式触摸屏
作者
Yuxiang Tang,Yijie Li,Kaiwen Zhou,Qi Luo,Xining Zhang,Yongda Ma,Zhiliang Hong,Jiawei Xu
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2025-10-31
卷期号:61 (6): 2809-2820
标识
DOI:10.1109/jssc.2025.3616622
摘要
This article presents a high-linearity, robust-jitter tolerance digital-to-analog converter (DAC) for high-fidelity audio systems. To improve the linearity, we propose a compact digital shaper utilizing a single vector quantizer (VQ) to mitigate both DAC mismatch and inter-symbol interference (ISI) with low system complexity. Two dummy current-steering DAC (IDAC) units are incorporated to further enhance linearity at high input levels. In addition, noise-shaped segmentation is used in the shaper and IDAC, which reduces hardware complexity and retains high signal-to-noise ratio (SNR) and linearity. Finally, the third-order digital delta–sigma modulator (DSM) has its coefficients optimized to improve IDAC jitter tolerance. Fabricated in a 0.18- $\mu $ m CMOS technology, this audio DAC achieves a state-of-the-art total harmonic distortion (THD) of −117.1 dB at −2.1 dBFS. By adopting resistive degeneration, optimized biasing current, and RC filter in the IDAC unit, this work exhibits a THD plus noise (THD + N) of −107.4 dB and an A-weighted dynamic range (DR) of 111.2 dB. Thanks to the optimized digital DSM, even under a 620-ps rms clock jitter, this DAC attains an excellent THD + N of −100.9 dB.
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