A 600V 8.7Ohmmm>sup<2>/sup<Lateral Superjunction Transistor

In this work we present for the first time experimental results and corresponding device simulations for high voltage lateral superjunction MOSFETs. We investigated experimentally various degrees of compensation for the lateral compensation structure and improved additionally the chip performance by optimizing the layout. We also realized different layouts in order to improve the chip performance. We show that a blocking voltage (BV) of 640V is achieved. Devices blocking above 600V achieve an on-resistance of 7.1Omega, which corresponds to a Rds,on times A of 8.7Omegamm ²