Optimization and Comparison of Specific ON-Resistance for Superjunction MOSFETs Considering Three-Dimensional and Insulator-Pillar Concepts

The optimization of drift region specific ON-resistance ( ${R} _{on,sp}$ ) for superjunction (SJ) MOSFETs with three-dimensional (3-D) and insulator-pillar ( ${i}$ -pillar) concepts is proposed and compared with the two-dimensional conventional SJ (2-D C-SJ) MOSFETs. With the constraints of avalanche breakdown and critical depletion, the optimized ${R} _{on,sp}$ and the corresponding design parameters are numerically determined. For the 3-D concept, a superior ${R} _{on,sp}$ can be obtained only for a high breakdown voltage (BV) or a low pillar aspect-ratio (AR) due to the better charge compensation. The junction field-effect transistor (JFET) effect induced by the lateral pillars depletion exceeds the charge compensation due to the stronger electric field crowding effect. For the ${i}$ -pillar concept, parasite depletion is alleviated due to an additional voltage sustained across the insulator pillar, especially for a narrow SJ pillar. The optimization design for the 650-V class SJ MOSFETs with 3-D and ${i}$ -pillar concepts demonstrates an optimized ${R} _{on,sp}$ with 3.99 $\text{m}\Omega \cdot $ cm ² at AR = 10 and 1.40 $\text{m}\Omega \cdot $ cm ² at AR = 70 can be obtained in 3-D ${i}$ -pillar SJ (3-D I-SJ) and 2-D ${i}$ -pillar SJ (2-D I-SJ), respectively. For the 650-V class SJ MOSFETs, 3-D and 2-D I-SJ structures have a lowest ${R} _{on,sp}$ than the other structures for AR less and greater than 57, respectively. The charge imbalance effects of BV for these structures are also discussed.