无杂散动态范围
有效位数
逐次逼近ADC
CMOS芯片
校准
抖动
线性
动态范围
功勋
计算机科学
电子工程
电容器
噪声整形
物理
电气工程
工程类
电压
计算机视觉
量子力学
作者
Jorge Lagos,Nereo Markulic,Benjamin Hershberg,Davide Dermit,Mithlesh Shrivas,Ewout Martens,Jan Craninckx
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2022-04-01
卷期号:57 (4): 1112-1124
被引量:12
标识
DOI:10.1109/jssc.2021.3133829
摘要
This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration. It leverages a novel SAR quantizer and narrowband dither injection to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) linearity and bias optimality. The ADC also includes an on-chip, wide-range, fully dynamic reference regulation system. Implemented in 16-nm CMOS, it consumes 3.3 mW at 500 MS/s (including regulation) and achieves 10.1 ENOB and 75.5-dB SFDR, resulting in Schreier and Walden figure-of-merit (FoM) values of 171.1 dB and 6.2 fJ/conv.-step, respectively.
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