Development of a Simple Verification Environment Using FPGA for image processing Hardware Created by High-Level-Synthesis Using TCP/IP

The development of image processing hardware using FPGA requires various peripherals such as cameras, memory, and displays. Commercially available FPGA boards have various peripherals, but they cannot be used without developing and implementing their own interface circuits. In addition, since the on-board peripherals are different for each FPGA board, new interface circuits must be developed every time when employing different FPGA boards. Therefore, we are developing a general-purpose verification environment that can be imported into commercial FPGA boards, including CPUs, without the need for peripherals on the FPGA board. The feature of the proposed verification environment is that it provides virtual peripherals on a PC. In addition, the proposed verification environment can directly mount hardware modules that are automatically converted from software programs by High-Level Synthesis (HLS). As a result, the design of interface circuits with peripheral devices can be omitted. In this paper, to realize the above verification environment, we developed the software to be executed on the PC and the CPU on the FPGA board, respectively. The communication between the PC and FPGA was initially implemented using serial communication, but in this paper, Linux is installed on the FPGA board’s CPU, and TCP/IP communication is implemented between the PC and FPGA. Using these software, we investigated whether it is possible to verify images such as 4K for the image processing hardware created by HLS.