Digital Equalization With ADC-Based Receivers: Two Important Roles Played by Digital Signal Processingin Designing Analog-to-Digital-Converter-Based Wireline Communication Receivers

Wireline input/output (I/O) bandwidth demand within networks in large data centers has increased rapidly over the last decade because of the explosion in data generation from cloud computing, mobile devices, and Internet of Things applications. To support this, both the number of I/O lanes per component and the per-lane data rate have continuously scaled up. For example, Figure 1 shows that the aggregate bandwidth of a typical large Ethernet switch application-specified integrated circuit (IC) has increased by an order of magnitude roughly every five years, starting at about 240 Gb/s with 24 channels operating at 10 Gb/s in 2008 and projected to near 25.6 Tb/s with 256 channels operating close to 100 Gb/s in 2019 [1]. This has led to the development of the current serial I/O standards at 56 Gb/s and planned future links operating in excess of 100 Gb/s.