High Throughput FPGA Implementation of LDPC Decoder Architecture for DVB-S2X Standard

This paper is devoted to the design of a decoder structure for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes of the DVB-S2X standard. The quasi-cyclic form of the matrix representation is the most convenient for the hardware implementation of the LDPC decoder, so the matrices of the DVB-S2X standard are converted to the QC form. The implementation of an LDPC decoder for the DVB-S2X standard is a challenging task, especially because of the long code words and large parity-check matrices. We propose a highly parallel FPGA implementation of LDPC decoder design based on the layered architecture and Min-Sum decoding algorithm. The structure of the decoder consists of 360 parallel cores responsible for the sequential calculation of variable-to-check (VTC), check-to-variable (CTV) messages and update posterior probabilities (APPs). Block RAM memory was used to store intermediate values of APP and CTVs. The decoder design is applicable to all code rates and allows to achieve throughput up to 500 Mbps at a clock frequency of 250 MHz