10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM

Advanced wireless transceivers exploit high-order modulation schemes to increase data-rates and call for high-spectral-purity frequency synthesizers. To serve this purpose, a fractional-N PLL that removes the time quantization error between the reference and divider signals through a digital-to-time converter (DTC) can be used, a technique which is now widespread among high-performance PLLs (Fig. 10.1.1 top) [1]. However, non-idealities, such as the DTC non-linearity and noise, degrade spectral purity, appearing either as fractional spurs or higher in-band phase noise in the PLL spectrum. Thanks to its simplicity and superior power-jitter trade-off, a variable-slope DTC (VS-DTC) is one of the most used DTC topologies [2–5]. Unfortunately, its linearity is affected by the slope-dependent propagation delay, T2, of the output stage. This causes an integral non-linearity (DTCINL) with a downward concavity (Fig. 10.1.1 bottom-left) [6]. The DTCINL is typically improved by adding a fixed capacitance, CFIX, at the output of the first stage, which reduces the voltage slope variation [4]. This method essentially trades a better DTC linearity for higher DTC phase noise (DTCPN) and power consumption. A similar trade-off exists in an alternative DTC architecture, i.e., the constant-slope DTC, that achieves better linearity by keeping a constant voltage slope at the input of the output stage [6] at the cost of a worse power-jitter product [5]. This work introduces a DTC topology, denoted as reverse-concavity variable-slope DTC (RCVS-DTC), which breaks the power-jitter-vs-linearity trade-off. The concept is demonstrated in an 8.75GHz fractional-N digital PLL achieving 57.3fs integrated jitter, a fractional spur of −63.4dBc, and a −252.4dB FoM.