ITRS: The International Technology Roadmap for Semiconductors

In a move singular for the world’s industry, the semiconductor industry established a quantitative strategy for its progress with the establishment of the ITRS. In its 17th year, it has been extended in 2009 to the year 2024. We present some important and critical milestones with a focus on 2020. Transistor gate lengths of 5.6 nm with a 3 sigma tolerance of 1 nm clearly show the aggressive nature of this strategy, and we reflect on this goal on the basis of our 10 nm reference nanotransistor discussed in Sect.3.3. The roadmap treats in detail the total process hierarchy from the transistor level up through 14 levels of metallic interconnect layers, which must handle the signal transport between transistors and with the outside world. This hierarchy starts with a first-level metal interconnect characterized by a half-pitch (roughly the line width) of 14 nm, which is required to be applicable through intermediate layers with wiring lengths orders of magnitude longer than at the first local level. At the uppermost global level, the metal pattern has to be compatible with high-density through-silicon vias (TSV), in order to handle the 3D stacking of chips at the wafer level to achieve the functionality of the final chip-size product. At the individual wafer level, the full manufacturing process is characterized by up to 40 masks, thousands of processing steps and a cumulative defect density of hopefully <1/cm².