A reconfigurable analog VLSI neural network architecture with non linear synapses

In this paper a reconfigurable analog VLSI neural network architecture is presented. The analog architecture implements a Multi-Layer Perceptron whose topology can be programmed without any modification of the off-chip connections. The architecture is scaleable and modular since it is based on a single-chip configurable basic module. To obtain a robust behaviour with respect to noise and errors introduced in the computation by analog circuits, we use non-linear synapses and linear neurons as neural primitives.