Flash Memory-Based Synaptic Device Using TFET for Neuromorphic Applications with Positive Weight Quantization

With the rapid advancement of artificial intelligence (AI), reducing the fan-in-induced current and power overhead in synaptic arrays has become a key challenge for neuromorphic hardware. This work proposes a NOR flash-based double-gate tunneling field-effect transistor (TFET) synaptic cell that directly addresses this issue. By exploiting the ultralow read current of TFET, the proposed device mitigates excessive cumulative current under large fan-in while maintaining sufficient read margin. The double-gate structure provides independent access paths for the top and bottom gates, enabling cell-level potentiation and depression within NOR architecture. Using an Incremental Step Pulse Programming/Erasing scheme, the device achieves highly linear 256-level analog weight modulation, which is then mapped to a positive-weight neural network model through a dedicated weight-shift and quantization strategy. The practicality of this approach is validated by reproducing a convolutional neural network (CNN) for Fashion-MNIST image classification on the proposed synaptic hardware model, where the inference accuracy closely tracks that of the original software model and even improves by approximately 0.06%. The reproduced accuracy closely matches that of the original software model without noticeable degradation, demonstrating its potential applicability in real-world scenarios. These results demonstrate that the proposed TFET-based double-gate flash synapse provides a viable device and mapping framework for low-power, high-fan-in neuromorphic systems.