Post-developed defect in word-line SADP process

A post-developed defect unlike the traditional satellite spot was found in the self-aligned double patterning (SADP) process flow. The defects tend to happen around boundary adjacent to the clear pattern area and finally yield pattern distortion or bridging (called "distortion" hereafter). This distortion defect has been characterized as yield killer since it causes word-line bridging after etching. This paper will describe the effect of resist type, top anti-reflective coating (TARC), various development puddle/rinse schemes, hard bake (HB) and advanced defect reduction (ADR) function on the distortion defect performance. TARC has been indentified as an effective solution to reduce the conventional satellite defect but the experimental result on eliminating the distortion defect is not obvious. In resist processing, post-developed HB temperature showed strong correlation to the distortion defect count. The distortion defect reduces as lowering the HB temperature, and furthermore the defect can be fully eliminated by experimentally skipping the HB step. The combination of multiple cycles of wafer agitation in the development puddle, double development puddle and scanning rinse significantly suppresses the defect count. However, the aggressive development recipe has made the process time too long to be acceptable for mass production. To minimize the throughput loss, ADR is another solution to eliminate the distortion defect.