CSFEM-YOLO: cross-scale fusion enhanced YOLO chip surface defect detection

Abstract Vision-based detection of chip surface defects is a key technology for automated inspection in the electronics manufacturing process. However, chip surface defects have similar interclass significance features and large intraclass scale differences, resulting in high false-negative and false-positive rates. For this reason, this paper proposes CSFEM-YOLO, which is an enhanced YOLOv8n model designed to select chips with good quality. The model integrates the CSFEM cross-scale fusion enhancement module, where the CSFEM module integrates the MSAFM multiscale attention fusion module and the DBFE dual-branch feature enhancer. The feature fusion mechanism and feature weighting mechanism are used to enhance the model feature expression capability to reduce the problem of missed and false detection of defects on the chip surface, thus improving the model detection accuracy. In addition, the use of MobileNetV3-Large for the backbone part of the network enables the model to improve the detection accuracy based on the amount of computation without a large increase. For validation, we use three chip surface defect public datasets: DAR, DBR, and GC10-DET. The experimental results show that CSFEM-YOLO outperforms the original YOLOv8n model, with an increase of 4.8%, 5.8%, and 4.2% in mAP on the three chip defect datasets, respectively. With only a 0.2M increase in parameters, it maintains a computation cost (7.1G FLOPs) close to the original model, meeting real-time detection requirements. This demonstrates its effectiveness in chip surface defect detection tasks.