计算机科学
可靠性(半导体)
可靠性工程
电路可靠性
可靠性理论
信号处理
集成电路封装
电子工程
算法
工程制图
作者
Yesin Ryu,Byungwoo Bang,Jaeho Shin,Hunseong Choi,Yoojin Kim,Hanum Ko,Jungrae Kim
标识
DOI:10.1109/tc.2026.3703497
摘要
As High Bandwidth Memory (HBM) continues scaling to address the demands of data-intensive workloads and AI-driven applications, ensuring resilience against increasingly frequent memory faults has become critical. DieCARE introduces a novel memory architecture co-designed with an innovative Error Correcting Code (ECC) scheme to enable die-level fault tolerance without requiring additional dies. It strategically distributes data and ECC check bits across multiple dies, leveraging advanced ECC techniques with flexible symbol layouts to optimize error correction capability, latency, and area efficiency.System-level evaluations demonstrate that DieCARE reduces memory Failure In Time (FIT) rate by 12, 000×, while maintaining an extremely low Silent Data Corruption (SDC) rate. These reliability improvements translate into increased system availability, yielding substantial benefits for large-scale computing systems.
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