材料科学
晶体管
光电子学
场效应晶体管
半导体
稳健性(进化)
可扩展性
阈下传导
载流子
纳米技术
电子迁移率
CMOS芯片
电子工程
阈下摆动
逻辑门
阈下斜率
MOSFET
半导体器件
电荷(物理)
薄膜晶体管
电气工程
电路设计
计算机科学
工艺CAD
金属浇口
设计要素和原则
工程物理
作者
Jinhyeok Pyo,Junsung Byeon,Jungmoon Lim,Sohyeon Park,Sungsan Kang,Byeongchan Kim,Gyuhwi Jeong,Haerim Kim,Bongjun Kim,SeungNam Cha,Sangyeon Pak
标识
DOI:10.1002/adfm.202525881
摘要
ABSTRACT Efficient carrier transport is a key requirement for designing high‐performance field‐effect transistor (FET) based on 2D transition metal dichalcogenides (TMDs). However, the unique structural characteristics of 2D semiconductors, which differ fundamentally from conventional 3D semiconductor materials, necessitate device architectures that deviate from traditional design approaches. Here, we propose a Bottleneck‐free Asymmetric Transistor Architecture (BATA) specifically tailored for 2D structures. Through technology computer‐aided design (TCAD) simulations, we reveal that adopting an embedded‐channel configuration at the source region maximizes charge carrier injection, while implementing a side‐channel configuration at the drain effectively mitigates the carrier transport bottleneck. Guided by this structural insight, we fabricated MoS 2 ‐based BATA devices that achieved near‐ideal subthreshold swing (SS) of approximately 60 mV/dec and field‐effect mobilities exceeding 200 cm 2 /V‐s, thereby demonstrating structurally enabled performance improvements over conventional FET. Furthermore, experimental validation of drain‐architecture‐dependent carrier transport bottlenecks was performed using mid‐voltage measurements and a single‐source dual‐drain asymmetric contact configuration. Finally, large‐scale integration was demonstrated through a 100‐device MoS 2 BATA array fabricated on a 2‐inch HfO 2 /Si wafer, confirming the robustness and scalability of the architecture. The BATA establishes a foundation for advancing 2D semiconductor‐based FET from laboratory demonstrations toward practical, fab‐compatible technologies.
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