A High-reliable and High-speed All-Digital STT-MRAM Based Computing-in-Memory for Binary Neural Networks

Computing-in-Memory (CiM) has been regarded as a promising AI accelerator architecture owing to its high energy efficiency and high throughput. This work proposes a novel STT-MRAM based CiM architecture for binary neural networks to address the limitations in analog STT-MRAM based CiM designs, which suffer from limited tunnel magnetoresistance (TMR) in magnetic tunnel junctions. The key improvements to the proposed architecture are as follows: (1) accelerated binary multiplication via a differential-type architecture; (2) improved tolerance to TMR through a digital multiplication readout scheme; (3) reduced power consumption owing to the high-speed computation. SPICE simulation shows that the proposed CiM cell can achieve a 0.68 ns low computing delay at a supply voltage of 1 V and 10 fF output parasitic capacitance, and 3 times increase in output swing at a TMR of 50%.