Investigation into the manipulation of non-uniformity and undercut features of a positive profile through silicon via

The key enabling technology for 2.5D and 3D packaging applications is the through silicon via (TSV), this device allows integrated circuits and additional component layers to be vertically stacked, this minimises internal signalling lengths allowing for faster operation, reduced heat production and lower power consumption. TSV’s are commonly formed with a positive profile structure which minimises conductor deposition defects in downstream production stages. This research was carried out on an SPTS Technologies Ltd Pegasus™ deep silicon etcher employing a single step O2/SF6/Ar process. The aim was to identify a predictable set of process parameters that can be used manipulate the dimensions of the ‘undercut’ feature that regularly forms at the top of the TSV profile during dry plasma etch processing. An L16 (4^5) Taguchi Array was used to determine the interaction effects of changing five critical process parameters on the undercut feature dimensions. The results from the process sample runs were analysed using commercially available statistical analysis software to investigate any predictable interactions between process parameter values and TSV profile dimensions. The outcome showed that there were no relationships that would facilitate predictable manipulation of the undercut dimensions. However, a clear and predictable trend was observed from the results which showed that increasing the wafer platform temperature results in a decrease in across wafer non-uniformity of critical TSV profile dimensions.