The Metal Gate Cut Process Development

The technology of FinFET has led to the continuity of device scaling and enabled the prolongation of Moore’s Law towards the 7 nm and beyond nodes. The gate cut last has been widely adopted since it can provide better SiP/SiGe growth environment, hence yielding the better electrical performance. However, this approach requires more complex process engineering at 3D structure. Both perfect physical structure and good electronic performance are challenging for gate cut last process. As is well known, the metal gate cut process is the only choice of 5nm FinFET and GAA FinFET, which directly determines the performance of FinFET. At present, the metal gate cut process has suffer the following difficulties: the Critical Dimension of the metal gate is only about 20nm, the height is over 100nm, and the aspect ratio has exceeded the limit of the most advanced etching tool; the metal gate complex composition, including more than 10 kinds of metal and insulation materials; the cut CD is very small, but the profile requirement is very challenging, all the metal layers are vertical, and the same CD is maintained from top to bottom. The bigger challenge is that the line end of metal gate cut is very close to germanium silicon or phosphor silicon. On the other hand, the metal's easy collection of charge and conduction will greatly increase the plasma induce damage risk, which needs to be controlled by properly selecting photo and etching conditions. We will start a study on the above issues and discuss the development direction and research ideas in each aspect. This manuscript will focus on plasma etching development during metal gate cut process. The CD shrinkage is very critical process in the soft mask etching process so as to break through the exposure limit of the immersion lithography. In general, immersion lithography with negative photoresist can not complete less than 40 nm CD, but gate cut, especially metal gate cut CD need as small as 20 nm. This puts forward very high requirements for soft mask etching. On the one hand, etch stop or defect cannot be caused with the large CD shrinkage; on the other hand, the CD should meet the design requirements and the patterning should be complete. We use the CxHyFz as etching gas with the advanced coupled plasma etching tool.We found the high/low bias pulsing scheme can reach balance on all sides, as the CD shrinkage, defect control, pattern transfer, line width roughness, the optimum process window. Another part will focus on metal cut etching process, cycle model is benefit to so many kinks of materials. Vertical profile show trade-off and ILD loss, we found the different design and requirement need to adopt different ILD remaining approach. At the same time, low Te etch process is key to avoid plasma induce damage.