Embedded Silicon Chip Capacitors in Glass Package for Vertical Power Delivery

This paper presents the design and fabrication of high-density ($>1,000 \mu \text{nF} / \text{mm}^{2}$), ultra-thin ($50-210 \mu ~\mathrm{m}$) multiterminal deep-trench silicon chip capacitors (DTCs) embedded in 100-300$\mu$m-thick glass substrate for vertical power delivery (VPD) in 3D stacked integrated voltage regulators (IVRs). Glassembedded high-density passives enhance power distribution network (PDN) performance. However, achieving optimal VPD requires precise design and fabrication to mitigate equivalent series inductance (ESL) and equivalent series resistance (ESR) from embedding DTCs in glass and minimize loop inductance from interconnections to IVR components. This work evaluates two DTC embedding approaches in glass substrate: (1) single-step microvias with horizontal copper interconnections, which simplify fabrication but increase parasitic, and (2) two-layer stacked microvias with copper plate interconnections, enabling direct vertical connections, reducing parasitic inductance from 1.2 nanohenry ($\mathbf{n H}$) to below 10 picohenry ($\mathbf{p H}$). Additionally, through-glass vias (TGVs) between parallel embedded capacitors (eCAPs) provide multi-layer interconnections with$60-80 \mu ~\mathrm{m}$radius vias ensuring manufacturability. Fabrication and experimental characterization are presented for one of the designs. The target is to achieve a total capacitance of 300 microfarads ($\mu \mathrm{F}$) with parallel DTC dies, capacitance densities up to$2,000 \text{nF} / \text{mm}^{2}$, and achieve low ESR ($\leq 10 ~\mathrm{m} \Omega$) and low ESL ($\leq 1\ \text{pH})$for each embedded DTC.