Noise margin criteria for digital logic circuits

Techniques for evaluating the noise margin for families of digital logic circuits are discussed and evaluated. It is shown that the technique of evaluating the -1 slope points on the inverter transfer function as used in most modern textbooks is not a valid and reliable approach to evaluating noise margin values. It is argued that the most reliable and reasonable criterion is to maximize the product of the two noise margins. This is equivalent to maximizing the area of a rectangle embedded within the loop formed by the transfer curves of an inverter pair. Most of the material presented can be found in the early literature on noise margin. However, because of the widespread use of the -1 slope criterion in modern textbooks, it is believed that a reexamination of basic approaches to noise margins is in order.< >