High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm

This paper describes an integral nonlinearity (INL) testing algorithm of a high-resolution low-sampling-rate Δ∑ analog-to-digital converter (ADC) in short time. The nonlinear curve of the DC input-output characteristics of the Δ∑ ADC can be obtained using a DC input, but it takes a long time; then it is not practical for mass production low-cost testing. So we consider a polynomial model of the Δ∑ AD modulator input-output characteristics and estimate its coefficient values from the fundamental and harmonics power by applying a cosine input and obtaining the modulator 1-bit output power spectrum with FFT. Our simulation and experimental results show that significant testing time reduction can be achieved with the proposed method.