Parasitic Inductance Design for Preventing Oscillatory False Triggering of Parallel-Connected GaN-FETs

GaN-FETs are recently spreading in high-power switching converters, where GaN-FETs are commonly parallel connected to switch the large current. However, the parallel-connected GaN-FETs often suffer from false triggering because the parallel connection incorporates multiple LC resonators of the parasitic capacitance of GaN-FETs and the parasitic inductance of the printed circuit board, which can be easily excited by the switching noise and fluctuate the gate voltage. Particularly, GaN-FETs are susceptible to the self-sustaining repetition of the false triggering, i.e. the oscillatory false triggering, which must be prevented in industrial products. For prevention of this phenomenon in the case of a single GaN-FET, the preceding studies have proposed the design instruction of the parasitic inductance. However, few insights are available for the parallel-connected GaN-FETs. The purpose of this paper is to elucidate the design instruction to prevent the oscillatory false triggering for parallel-connected GaN-FETs through analyzing the equivalent circuit model of this phenomenon. The result revealed that parallel-connected GaN-FETs need the design instruction slightly modified from that for a single GaN-FET. The appropriateness of this modified instruction was verified by the simulation, suggesting the feasibility of this instruction for applying the parallel-connected GaN-FETs in high-power switching converters.