Gate controlled magnetoresistance in a silicon metal-oxide-semiconductor field-effect-transistor

We present a study of the magnetoresistance (MR) of a Si metal-oxide-semiconductor field-effect-transistor (MOSFET) at the break-down regime when a magnetic field is applied perpendicular to the plane of the device. We have identified two different regimes where we observe a large and gate-voltage dependent MR. We suggest two different mechanisms which can explain the observed high MR. Moreover, we have studied how the MR of the MOSFET scales with the dimensions of the channel for gate voltages below the threshold. We observed a decrease in the MR by two orders of magnitude by reducing the dimensions of the channel from 50×280 μm2 to 5×5 μm2.