Dynamic On-Resistance Degradation in E-Mode GaN HEMTs Under Over-Voltage Hard Switching Stress: Insight of Physical Space and Energy Levels

This study investigates the degradation of dynamic on-resistance ($\mathrm{R}_\text{on}$) in P-GaN gate enhancement-mode high-electron-mobility transistors (HEMTs) under hard-switching (HSW) stress. Devices were stressed under over-voltage conditions to accelerate degradation. After HSW stress, the dynamic $R_{\text {on }}$ increased significantly under a drain-to-source bias ($V_{\text{ds}}$) ranging from 0 V to 500 V, indicating stress-induced defect formation and charge trapping. To analyze the physical distribution of charge trapping, output capacitance ($C_{\text {oss }}$) - $V_{\text {DS }}$ measurements, combined with TCAD simulations, provide evidence of impact ionization followed by electron and hole accumulation in different field plate (FP) regions. To examine the energy levels of stress-induced traps, current deep-level transient spectroscopy (I-DLTS) revealed a reduction in trap activation energy ($E_{\mathrm{a}}$) of post-HTOL stressed sample, indicating that hot-carrier modified the defects energy and migrate them closer to the conduction and valence bands. These findings provide critical insight into the physical locations and energy levels of degradation trapping sites after HSW stress, aiding device optimization and long-term switching reliability assessment.