Universal Compact Model of Flicker Noise in Ferroelectric Logic and Memory Transistors

In this article, we present a physics-based compact model of flicker noise (low-frequency noise) in ferroelectric (FE) field-effect transistors (FETs). This model predicts the noise due to charge trapping/de-trapping in the FE/dielectric interface accounting for both carrier number fluctuations and correlated mobility fluctuations in the channel. This model can work with any FE framework and has been tested with Landau based as well as nucleation-limited-switching (NLS)-based cores. The effect of FE thickness scaling is also captured. The model is validated for both logic and memory devices with TCAD as well as experimental measurements.