热压连接
球栅阵列
材料科学
热膨胀
包对包
中间层
小型化
芯片级封装
模具(集成电路)
引线键合
机械工程
复合材料
光电子学
炸薯条
图层(电子)
纳米技术
蚀刻(微加工)
电气工程
薄脆饼
工程类
焊接
晶片切割
作者
Vidya Jayaram,Scott McCann,Ting‐Chia Huang,Satomi Kawamoto,Raj Pulugurtha,Vanessa Smet,Rao Tummala
标识
DOI:10.1109/ectc.2016.384
摘要
Increasing needs for functionality, performance and system miniaturization in fine-pitch consumer applications have been driving a new class of ultra-thin interposers and packages with larger body sizes, aggravating warpage. These trends gave rise to serious concerns for assembly yield and reliability, especially at board level. The recent adoption of substrate technologies with silicon-matching coefficient of thermal expansion (CTE) reinforces these concerns by introducing a large CTE mismatch between package and organic board. Warpage control and mitigation in assembly has, therefore, become critical in enabling reliable SMT interconnection of ultra-thin, large, low-CTE BGA packages to the board. Copper pillar thermocompression bonding (TCB) has emerged as a key assembly technology to improve die assembly yield at pitches below 80µm and large die sizes. In TCB, heat is applied from the die side only while the substrate is maintained at a low stage temperature, as opposed to isothermal heating in mass reflow. The temperature gradient in the package can, therefore, be finely tuned providing control over the warpage behavior. This paper investigates TCB-induced warpage and its dependence on the bonding thermal profiles in a single-chip, 200µm-thick, low-CTE organic package at 50µm pitch and 17mm x 17mm body size. Warpage trends as a function of the stage temperature were first predicted with a simple coupled thermal-structural finite-element model, then experimentally validated by Shadow-Moiré measurements of assemblies built with varying stage temperatures from 70°C to 150°C. Interactions with the thermocompression tool, in particular the effect of vacuum-coupling of the substrate to the stage, were considered and investigated. Guidelines for design of TCB profiles for warpage minimization were finally derived with considerations of assembly throughput to improve board-level SMT yield and system-level reliability.
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