An Energy Efficient 4-bit SRAM Compute-in-Memory Macro With Tunable Reference Charge Injection SAR ADC

In this article, an SRAM-based analog compute-in-memory (CIM) macro is presented that is designed to process multiply-accumulate (MAC) operations on 4-bit inputs and 4-bit weights encoded in a sign-magnitude format for convolutional neural network (CNN) inference. A charge-sharing 4-bit compute cell is proposed which performs multiplication between a 4-bit input and a 4-bit weight and stores the result on a unit capacitor for accumulation with other cells in the channel. The macro can effectively perform vector-matrix multiplication (VMM) on 32, 64, 96, or all 128 compute cells in a channel. This design flexibility allows the macro to deploy CNN kernels of different sizes which improves macro utilization. To minimize the power consumption of the analog-to-digital converter (ADC), the parasitic interconnect capacitance of the MAC lines is used as an integrating capacitor in the charge injection DAC. A 6-bit charge-injection SAR ADC is implemented which features a digitally controlled tunable reference, essential for converting the pre-ADC MAC value to its digital equivalent without gain error. The proposed design is implemented and fabricated in 65-nm low power CMOS process with a silicon footprint of 0.13 mm2. The macro achieves an energy efficiency of 85.8 TOPS/W and an area efficiency of 2.62 TOPS/mm2.