The improvement of layout dependent Cu filling defect

Abstract The downscaling of logic devices has posed numerous engineering and manufacturing challenges in copper (Cu) interconnections. The primary failure modes of Cu filling defects are narrow top openings and discontinuous Cu seeds on sidewalls. This study investigates the influence and mechanism of layout on Cu filling defects. Dense line wires with uneven local layouts are prone to defects, which is attributed to the altered distribution of additives in electrochemical plating (ECP), leading to differences in bottom-up filling behavior. It is demonstrated that large-sized metal conductor regions adjacent to dense line wires adsorb substantial amounts of suppressor, resulting in sparse current density in these areas. Given the fixed total local current density, the sparseness of current density in adjacent regions inevitably diverts more current lines to the dense line wire areas. The excessive current density exceeds the local redistribution capacity of additives, causing premature sealing of trench tops and the formation of void defects. A low-current plating process significantly mitigates these defects but may compromise the protective capability of the Cu seed. Additionally, the perimeter density of the layout serves as an effective evaluation index.