Parasitic Resistance Influence on High Resolution Digitally Programmable Potentiometers Linearity

This paper describes the effect that parasitic resistances have on the accuracy of a high resolution digitally programmable potentiometer that is based on a multistage architecture. Experimental results available from silicon implementation in a 0.18μm EEPROM process of a nonvolatile 8-bit resolution digital potentiometer show a maximum value of about 0.25LSB for both non-linearity errors (INL and DNL). Unusual transitions found in the measured INL waveform, but also unexpected spikes in the measured DNL waveform were confirmed through simulations to be the cause of a parasitical resistance introduced by a long metal wire connection between two unit resistors in the wiper array layout.