Fast and low power TLB access mechanism with prediction buffer

This paper proposed a fast and low power TLB access mechanism with prediction buffer based on memory access locality principle,and designed a two-level TLB structure implemented by SARM instead of CAM to achieve fast access of the full associated TLB.Between the two levels of the introduced TLB,an independent and hardware configurable prediction buffer was designed to dynamically predict the access sequences of the second level TLB,which could reduce its access penalty when the first level TLB missed and significantly reduce the dynamic power consumption with little control logic.Experiment shows that compared with the traditional two-level TLB structure,the average access cycles of the second level TLB are about 20% of the traditional one,with only 1.81% area increment,which support low power and low cost embedded application.