Optimum low-voltage silicon power switches fabricated using scaled trench MOS technologies
作者
K. Shenai,W. Hennessy,M. Ghezzo,C.S. Korman,H-R Chang,V.A.K. Temple,M.S. Adler
标识
DOI:10.1109/iedm.1990.237042
摘要
Optimum low-voltage silicon power MOSFET technologies with forward conductivities approaching the silicon limit are presented. Vertical scaled trench power MOSFETs with measured performances of V/sub DB/=55 V (R/sub sp/=0.2 m Omega -cm/sup 2/, k/sub DEV/=5.7 Omega pF) and V/sub DB/=35 V (R/sub sp/=0.15 m Omega -cm/sup 2/, k/sub DEV/=4.3 Omega -pF) were developed, where V/sub DB/ is the drain-source avalanche breakdown voltage, R/sub sp/ is the specific on-state resistance, and K/sub DEV/ is the input device technology factor. Measured performances are in excellent agreement with detailed two-dimensional device simulations.< >