Packaging and Test of Photonic Integrated Circuits (PICs)

Packaging and test of Photonic Integrated Circuits (PICs) have been dramatically changing in the last years, as the applications addressed by PIC-based modules require a shift to mass manufacturing. It leads to new and more challenging requirements for the packaging and test of PICs, which are expected to converge to approaches similar to CMOS microelectronics, with high throughput and yield. However, packaging and test of PICs still need to address several well-known critical requirements such as accurate alignment (laser/PIC and PIC/fiber coupling) or thermal management due to the thermal sensitivity of the alignment and photonic devices, and efficient co-packaging of the photonic circuits together with electronic drivers and host chips. This chapter deals with different optical packaging techniques as well as the underlying theory, examining current trends and requirements from emerging applications and architectures of PIC-based modules: co-packaged modules or photonic interposers among others. It also examines the evolution of the ecosystem, especially the assembly and test equipment evolution and PIC design environment.