VLSI Realization of Fast Fourier Transform using Multipath Butterfly Unit Based Iterative ICORDIC

Fast Fourier transform (FFT) is an essential mechanism in many communication systems, including 4 G and 5 G. The hardware performance of these communication systems is dependent on the FFT complexity. However, conventional very large-scale integration (VLSI)-based FFT methods have failed to reduce area, delay, and power consumption. Therefore, this study focused on the development of a multipath-based iterative ICORDIC-based FFT (MPIC-FFT). Initially, the input data are applied to the controller block, which is used to monitor all other modules. Furthermore, the input data monitored by the controller are used to write data and are applied to ternary content address memory (TCAM). Here, the address generator module contains true random number generators (TRNG), which develop read and write addresses using linear feedback shift registers. In addition, the TCAM module is used to store the write data with respect to the write address and produce read data for the multipath butterfly unit (MPBU) module. The ICORDIC is the major core unit of the MPIC-FFT, which generates synchronous twiddle factors using rotation properties. Later, the MPBU block performs mathematical Fourier operations on read data and twiddle factors, which reduces the number of iterative cycles for twiddle factor generation. Finally, the output signal was generated from the MPBU block. The simulations show that the proposed MPIC-FFT uses 206 slice registers, a 0.670 ns delay, and 0.122 watts of power. The performance comparison shows that the proposed MPIC-FFT resulted in a reduced area, delay, and power consumption compared to the other methods.