计算机科学
高级合成
加速
NIST公司
现场可编程门阵列
密码学
软件
标准化
算法
桥接(联网)
编码(集合论)
逻辑综合
量子计算机
计算机工程
嵌入式系统
并行计算
量子
逻辑门
程序设计语言
操作系统
物理
自然语言处理
集合(抽象数据类型)
量子力学
计算机网络
作者
Andrea Guerrieri,Gabriel Da Silva Marques,Francesco Regazzoni,Andrés Upegui
标识
DOI:10.1109/dsd57027.2022.00109
摘要
High-level synthesis is a mature Electronics Design Automation (EDA) technology for building hardware design in a short time. It produces automatically HDL code for FPGAs out of C/C++, bridging the gap from algorithm to hardware. Nevertheless, sometimes the QoR (Quality of Results) can be sub-optimal due to the difficulties of HLS in handling general-purpose software code. In this paper, we explore the current difficulties of HLS while synthesizing Lattice-based Post-Quantum Cryptography (PQC) algorithms. We propose code-level optimizations to overcome the limitations of high-level synthesis increasing the QoR of generated hardware. We analyzed and improved the results for the algorithms competing in the 3rd round of the NIST standardization process. We show how, starting from the original reference code submitted for the competition, original performance and resource utilization can be improved, in some cases with a speedup factor up to 200 x or an area reduction of 80%.
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