Fabrication of segmented-channel MOSFETs for reduced short-channel effects

To facilitate continued CMOS technology scaling, thin-body transistor structures such as the FinFET [1] and fully depleted silicon-on-insulator (FD-SOI) MOSFET [2] have been proposed to better suppress short-channel effects (SCE) than the conventional MOSFET structure in the sub-25 nm gate length (Lg) regime. However, these structures require either more challenging fabrication processes or more expensive silicon-on-insulator substrates. Recently, a segmented-channel bulk MOSFET (SegFET) structure [3] was proposed as a more evolutionary solution that offers the advantages of a thin-body MOSFET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).