Cavity Substrate Technology for SIP Application with Passive Components

The application of SiP (System in Package) is increased because of its benefit of fast development and cost-effectiveness compared to SOC (System on Chip). Despite its strength, there is constant demand for reducing the form factor of SiP. WLP (Wafer-Level Package) or PLP (Panel-Level Package) usually provides smaller form factor than the conventional packages with substrates. However, when SiP requires passive components, which usually are very tall particularly for inductors, the competitiveness of thin interconnect layers of WLP or PLP diminishes. For these SiP, cavity substrate can be used to achieve the similar package thickness with better cost and proven assembly process. We present multi-layered cavity substrate technologies that we developed for Sip application.