Model-Based Variation-Aware Optimization for Offset Calibration and Pre-Sensing in DRAM Sense Amplifiers

This article proposes a new mathematical model that accurately predicts statistical margin characteristics of bit-line sense amplifiers (BLSAs) with offset calibration (OC) and pre-sensing (PS), while providing techniques to improve sensing margins. In particular, threshold voltage mismatch caused by reduced transistor sizes introduces sensing offsets, further degrading the already limited sensing margins under low-voltage conditions. While various BLSAs incorporating OC and PS techniques have been proposed to address these challenges, and studies have been conducted on models predicting statistical offset, previous research has not adequately considered OC timing ( $t_{OC}$ ) and transistor size effects. We independently model the OC, charge sharing (CS), and PS operations of DRAM BLSAs to accurately predict both deterministic and stochastic offsets resulting from various operation combinations. Notably, our model incorporates $t_{OC}$ dependency, which was not considered in previous models, and accurately analyzes transistor size effects through integration with Pelgrom’s equation. The primary advantage of the proposed model lies in its design optimization efficiency. While HSPICE simulations combining Monte Carlo (MC) and binary search methods require numerous iterations for single design point verification, our model significantly reduces design time by effectively narrowing the region of interest through pre-optimization using statistical characteristics. Furthermore, the model’s general form demonstrates high practicality through easy application to various BLSA types based on OC scheme types and PS operation presence. In conclusion, this article presents optimal design guidelines by accurately predicting deterministic and stochastic offset characteristics according to $t_{OC}$ and transistor size ratios, showing high correlation with HSPICE MC simulation results.