An Efficient Training Methodology of Hardware Neural Network Based on Wafer‐Scale MoS2 Synaptic Array

Abstract Neuromorphic computing has attracted broad attention in recent years, owing to its break in the bottleneck of traditional von Neumann architecture with its advantages of high efficiency and low power consumption. However, many reported works only focused on the improvement of the performance of a single device, or assumed that each neuron in the artificial neural network (ANN) is ideal and equivalent, which cannot realize the application of device in hardware neural network (HNN). Herein, a top‐gate structured floating‐gate synapse (FG‐Synapse) array is fabricated. Wafer‐level molybdenum sulfide (MoS 2 ) channel and hafnium oxide (HfO 2 ) dielectric layer are grown by atomic layer deposition. Besides, long‐term potential/depression (LTP/LTD) performance of each device are explored, which showed high consistency. Finally, a three‐layer ANN and proposed as an efficient approximation method to realize the recognition of digital pictures. It is the first time that a 2D device array based on a floating gate structure applied to ANNs. The recognition rate of a single device reaches 92.2%, and the recognition rate of the device array reaches 91.3%. This work is of great significance to provide the possibility for the application of larger‐scale arrays in neuromorphic computing in the future.