A Novel Zigzag SRAM Bitcell Design in the Complementary FET Framework

This article proposes a novel zigzag-cell design for the six-transistor static random access memory (SRAM) bitcell in the complementary field-effect transistor (CFET) framework. The zigzag-cell design not only maintains the aggressive area reduction but also allows for shorter bitlines, directly benefiting from the circuit layout changes caused by the CFET architecture. The specific layouts of the zigzag-cell design are introduced by incorporating them into two process flows with different complexity. The first assumed process flow contains only the essential steps of CFET SRAM, and according to which the zigzag-cell bitcell can achieve an area reduction of more than 20% over the thin-cell bitcell. Moreover, the performance of zigzag-cell SRAM is also improved by 4.6% and 16.3% in read time and write margin, respectively. Following the second more complicated process flow, the zigzag-cell design does not offer further area reduction compared with the thin-cell design, but it needs fewer metal layers. The proposed design is a promising choice for the CFET SRAM bitcell layout.