| 标题 |
Stress Analysis and Design Optimization for Low- $k$ Chip With Cu Pillar Interconnection |
| 网址 | |
| DOI | |
| 其它 |
期刊:IEEE Transactions on Components, Packaging and Manufacturing Technology 作者:Fa Xing Che; Jong-Kai Lin; Keng Yuen Au; Hsiang-Yao Hsiao; Xiaowu Zhang 出版日期:2015-08-25 |
| 求助人 | |
| 下载 |
PDF的下载单位、IP信息已删除
(2025-6-4)