A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction

This paper introduces the third-generation High Bandwidth Memory (HBM3) HOST PHY, achieving a data rate of 7.2 Gbps per pin, designed on Intel 4 technology and utilizing embedded multi-die interconnect bridge (EMIB) based packaging. The design attains low energy efficiency (pJ/bit) through the use of unterminated N-N low swing transmitters and unmatched receive paths. To address N-UI supply-induced deterministic jitter, the entire clocking path is maintained under an internally generated linear voltage regulator (LVR). Advanced I/O training for PHY memory read/write operations is implemented using the proposed per bit deskew (PBD) for per pin eye optimization. Additionally, eye degradation due to temperature drift is mitigated in both write and read directions through a novel on-the-fly periodic sampling-point update mechanism, which operates without interrupting traffic.