Study on the fundamental factors of the property evolution of a 300 mm polycrystalline trap-rich layer

Abstract The geometry and resistivity of the trap-rich layer are key parameters for 300 mm trap-rich silicon-on-insulator (TR-SOI) wafers. In this paper, the evolution of the warpage and resistivity of poly-Si layers grown by atmospheric chemical vapor deposition with deposition temperature has been studied. The ability to quantify the surface grain size of undoped poly-Si was evaluated using scanning electron microscopy, electron backscattering diffraction, and transmission Kikuchi diffraction (TKD). With a resolution scale of several nanometers, the fine grains on the surface of poly-Si are accurately identified by TKD. It is confirmed that the decrease in compressive stress with deposition temperature is caused by the lower ratio of (110) grain orientation and the reduction of fine grains on the surface. However, when stress is released, the random grain boundaries (GBs) of poly-Si change into coincidence site lattice low-Σ GBs with low recombination activity, which greatly lowers the film bulk resistivity and reduces its capacity to trap charges. Thus, a process window for the manufacturing of 300 mm TR-SOI wafers is created by balancing the degradation of resistivity in the process of using deposition temperature to seek improvements in poly-Si warpage.