48V Power Delivery for AI Computing Systems: IVR-Oriented Architecture and Topology Selection

Integrated voltage regulators (IVRs) have become a critical enabling technology for next-generation computing power delivery, providing high power density, minimized distribution losses and fast transient responses. This work reviews IVR advances, including in-package integration strategies, high-density passive component development, and circuit design considerations. Furthermore, an IVR-oriented framework for front-end topology selection and multi-stage co-design is proposed to fully exploit IVR advantages. Specifically, IVRs implemented in low-voltage (LV) BCD or GaN technologies enable high-voltage, high-power delivery at 5-10 MHz, typically paired with transformer-based fixed-ratio topologies for high efficiency and cost-effectiveness. In contrast, advanced-CMOS-stacked IVRs support ultrafast transient responses at tens to hundreds of MHz, but require intermediate-bus-voltage (IBV) regulation to avoid device overstress. To address this, hybrid switched-capacitor merged multi-inductor topologies are adopted to enhance both power density and reliability. These insights provide corresponding topology-matching guidelines for future development of higher-efficiency, higher-density, and more reliable power-delivery architectures.