A high output resistance, wide bandwidth, and low input resistance current mirror using flipped voltage follower cell

Abstract The paper proposes a current mirror designed using the current sensor structure of class‐AB flipped voltage follower cell at the input stage and super cascode structure at the output stage. The proposed current mirror offers low input resistance due to the current sensor at the input stage and high output resistance due to super cascode configuration at the output stage. The proposed current mirror offers a good dynamic range of 0 to 300 μA with less copying error of 0.54%, wide bandwidth of 319.8 MHz, high output resistance of 19.8 GΩ, and low input resistance of 161.34 Ω. The proposed current mirror is designed using BSIM3V3 180‐nm CMOS technology and simulated using spectre in the Cadence Virtuoso analog design environment at room temperature. The Cadence Virtuoso layout XL editor has been used to design the physical layout of the proposed current mirror. The pre‐layout and post‐layout simulation results of the proposed current mirror have been shown to validate its performance. The Monte Carlo analysis has also been performed to analyze the effects of process variations and mismatches on the performance of the proposed current mirror.