Hole Current Enhancement Using W 1– x Cr x Se 2 Alloy Interface for p-Type WSe 2 FETs

High Resolution Image Download MS PowerPoint Slide Two-dimensional (2D) transition-metal dichalcogenides (TMDs) have emerged as promising candidates for next-generation semiconductor devices. Among TMDs, tungsten diselenide (WSe 2 ) is regarded as an ideal material for p-type field-effect transistors (FETs). However, the realization of high-performance p-type devices remains limited due to undesired ambipolar behavior and high contact resistance. These challenges originate from Fermi level pinning (FLP) caused during conventional deposition processes. Although van der Waals (vdW) contacts have been introduced to overcome FLP, their implementation faces difficulties due to contamination-induced degradation and limitations in CMOS process compatibility. In this study, we demonstrate a scalable approach for p-type contact via the W 1– x Cr x Se 2 alloy interface. It has been reported that Cr incorporation reduces the bandgap of WSe 2, while Cr x Se y exhibits p-type semimetal properties. Leveraging these properties, thermal annealing of Cr contacts enables the formation of WSe 2 /W 1– x Cr x Se 2 /Cr layers at the contact region. This interfacial alloy effectively suppresses FLP, eliminates undesirable ambipolar behavior, and enhances hole injection. The resulting devices achieve a Schottky barrier height as low as 61.1 meV and reduce contact resistance by approximately 3 orders of magnitude. Consequently, W 1– x Cr x Se 2 alloy interface contact WSe 2 FETs exhibit robust p-type performance with an average on/off current ratio of 2.19 × 10 8 across 20 devices. These findings present a practical and scalable strategy for engineering low-resistance p-type contacts in WSe 2, providing an important step toward the integration of TMD-based complementary logic in future scaled CMOS technologies.