An Analytical Threshold Voltage Model for Sige-Channel Pmos Devices

This paper reports an analytical threshold voltage model for SiGe-channel P&IOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical formula, with a higher germanium content, the threshold voltage of a SiGe-channel PMOS device tends to change toward the positive direction. With a thinner gate oxide or silicon cap, the threshold voltage shifts toward the positive direction. Summary SiGe-channel PMOS devices have been receiving lots of attention owing to their potential in achieving high performance [1][2]. Using a SiGe heterosturcture, a quantum well has been built in the PMOS device for improving its transconductance [Z]. Various SiGe-channel PklOS devices have been reported. However, no analytical threshold voltage models have been reported. For advanced SiGe-channel PMOS devices, their device structure can be complicated. An analytical threshold voltage model can be very helpful for device design. In this paper, an analytical threshold voltage model derived from Poisson's equation for PhlOS devices with a SiGe channel is described. Fig. 1 shows the cross section of the SiGe-channel PMOS device I21 under study. An iV+ polysilicon gate with an oxide thickness of l20A is used. Below the gate oxide, a SikOA cap of 50.3 is pfaced atop the undoped SiGe-channel of 20OA. Below the SiGe-channel, the substrate doping density is 1 x 10'6cm-3. The S/D junction depth is O.1pm. In order to simplifL the analysis, no interface charges are assumed. Fig. 2 shows the internal hole density distributions in the substrate direction in the center of the SiGe-channel PMOS device with a germanium concentration of 0.15,0.2,0.25 at VGS = -lV and VDS = -0.1V based on simulation results using a modified PISCES program [3] where SiGe induced bandgap narrowing has been included. As shown in Fig. 2, around the threshold voltage at VGS = -1V, the buried SiGe-channel dominates in all three cases. An increase in the germanium content leads to a large increase in hole density. Specifically, ac VGS = -lV as shown in dotted lines, for a germanium content of 0.15, 0.2, and 0.25, the peak hole density located at the top of the SiGe buried channel is 9.45 x 1015cm-3, 3.07 x 10'6cm-3, and 7.19 x 1016cm-3, respectively. In the depletion region below the SiGe channel (q < L < 14, solving Poisson's equation becomes: The threshold voltage of the PMOS device, which is defined as the gate voltage when the electrostatic potential at the top of the SiGe channel reaches df,,(~~) as defined in Eq. (1) in Fig. 3, is as shown in Eq. (2). Fig. 4 shows the internal potential distribution in the substrate direction in the PVOS device usingthe model and PISCES results. The PMOS device is with three Ge contents - 0.15,0.20,0.25 in the SiGe channel. A close fit between the model and simulation results can be observed. Fig. 5 shows the the threshold voltage vs. the Ge concentration in the SiGe channel of the PMOS device. For a SiGe-channel PMOS device with a larger germanium content, its threshold voltage tends to shift more toward the positive direction. In fast. the threshold voltage is proportional to the bandgap narrowing factor. A close match between the model and simulation results can be identified. As the silicon cap becomes thicker, the threshold voltage shifts toward the negacive direction. In addition, a thinner gate oxide may change the threshold voltage toward the positive direction.