WNxCy VT Tuning of Split Gate Nanosheet CFETs with Dual Work Function Metals Achieving 0.93 VT Match/Improved 0.24V Noise Margin/Record Gain of 61V/V

The sophisticated epitaxial growth and device fabrication process of dual-work-function-metal split-gate CFETs are demonstrated for the first time. Multiple P/N junctions are employed to isolate stacked transistors. The effective work function of$\mathbf{W N}_\mathbf{x} \mathbf{C}_{\mathbf{y}}$can be tuned by changing the N2/H2flow rate during the PEALD process. The ~10nm thick$\mathbf{W N}_\mathbf{x} \mathbf{C}_{\mathbf{y}}$are integrated into GeSi CFET to show the pFET threshold voltage tunability of 500mV. The dual-WFM split-gate CFETs can provide matched$\mathbf{V}_{\mathbf{T}}\left(\left\vert \mathbf{V}_{\mathbf{TP}}\right\vert /\left\vert \mathbf{V}_{\mathbf{TN}}\right\vert \mathbf{=0.93}\right)$. The hold state noise margin of SRAM is expected to be 0.24V at$\mathbf{V_{D D}=0.75} \mathbf{V}$. The voltage transfer curve of a CFET inverter has a record gain of 61V/V among monolithic nanosheet CFETs. The$\mathbf{W} \mathbf{N}_\mathbf{x} \mathbf{C}_\mathbf{y}\ \mathbf{V}_\mathbf{T}$tuning of 300mV is also demonstrated for the nFET.