An Empirical Modeling of Gate Voltage-Dependent Behaviors of Amorphous Oxide Semiconductor Thin-Film Transistors including Consideration of Contact Resistance and Disorder Effects at Room Temperature

In this paper, we present an empirical modeling procedure to capture gate bias dependency of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) while considering contact resistance and disorder effects at room temperature. From the measured transfer characteristics of a pair of TFTs where the channel layer is an amorphous In-Ga-Zn-O (IGZO) AOS, the gate voltage-dependent contact resistance is retrieved with a respective expression derived from the current-voltage relation, which follows a power law as a function of a gate voltage. This additionally allows the accurate extraction of intrinsic channel conductance, in which a disorder effect in the IGZO channel layer is embedded. From the intrinsic channel conductance, the characteristic energy of the band tail states, which represents the degree of channel disorder, can be deduced using the proposed modeling. Finally, the obtained results are also useful for development of an accurate compact TFT model, for which a gate bias-dependent contact resistance and disorder effects are essential.