NMOS逻辑
静电放电
电子工程
缩放比例
集成电路设计
计算机科学
逻辑门
电路设计
电气工程
电压
工程类
晶体管
几何学
数学
作者
M. Mergens,Koen G. Verhaege,Corbin Russ,John Armer,Phillip C. Jozwiak,G. Kolluri,L.R. Avery
出处
期刊:Electrical Overstress/Electrostatic Discharge Symposium
日期:2001-09-01
卷期号:: 1-11
被引量:42
摘要
A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in various implementations. It can be applied to (self-protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations with an ESD area performance up to 5VHBM/um2 can be realized both in fully silicided and silicide blocked NMOS designs.
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